1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display device and method that is capable of compensating for a step coverage at each location of a liquid crystal display panel.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) controls light transmissivity of liquid crystal cells arranged in a matrix pattern in response to a video signal to thereby display a picture corresponding to the video signal on a liquid crystal display panel. An active matrix LCD device includes a liquid crystal display panel having liquid crystal cells arranged and driving integrated circuits (IC's) for driving the liquid crystal cells. The driving IC's are usually manufactured as semiconductor chips. Driving IC's for a tape automated bonding (TAB) system are mounted on a tape carrier package (TCP) while driving IC's for a chip on glass (COG) system are mounted on the surface of the liquid crystal display panel. The driving IC's of the TAB system are electrically connected to a pad portion provided at the liquid crystal display panel by the TCP.
FIG. 1 is a plan view showing a conventional liquid crystal display panel. The LCD panel includes a lower plate 20 attached to an upper plate 4. In FIG. 1, the liquid crystal display panel includes a picture display part 10 having liquid crystal cells arranged in a matrix pattern. Gate pads 14 and data pads 32 are positioned at edges of the lower plate 20 without overlapping the upper plate 4 and connected to gate lines and data lines, respectively. In the picture display part 10, the data lines to each of which a video signal is applied and the gate lines to each of which a scanning signal, that is, a gate signal is applied are arranged in such a manner as to cross each other. At each of the crossing portions, a thin film transistor (TFT) is provided for switching the liquid crystal cell. A pixel electrode is connected to the TFT to drive the liquid crystal cell. The upper plate 4 is provided with a black matrix, color filters coated separately for each cell area and a common electrode that is a counterpart electrode to the pixel electrode. The upper plate 4 and the lower plate 20 are attached to each other by a sealant coated on a seal part 12 positioned at the periphery of the picture display part 10. A certain cell gap distance is defined between the upper plate 4 and the lower plate 20 by a height of the coated sealant. The space defined in this manner is filled with a liquid crystal and a constant cell gap distance is maintained with the aid of a spacer sprayed prior to an injection of the liquid crystal.
However, the above-mentioned conventional liquid crystal display device has a non-uniform cell gap because the structure of the lower plate 2 coated with the sealant is different at different locations thereof resulting in a step coverage. In particular, the cell gap distances at a gate link area and a data link area are relatively small.
Problems associated with the conventional device will be described with reference to FIGS. 2-6. FIG. 2 is an enlarged view of the gate link area crossing the seal part 12 in FIG. 1, and FIG. 3 is a section view of the seal part taken along the line A-A′ in FIG. 2. A gate link part 15 extending from a gate pad 14 consists of a gate link electrode 16, a gate insulating layer 22, an amorphous silicon layer 24, an amorphous silicon layer 26 doped with an impurity, hereinafter referred to as “n+layer”, and a protective film 28 disposed thereon. The gate link electrode 16 is formed integrally with the gate pad 14 and the gate line by depositing a gate metal material on the transparent substrate 20 and thereafter patterning it. The gate insulating layer 22, the amorphous silicon layer 24 and the n+layer 26 are sequentially formed on the transparent substrate 20 provided with the gate link electrode 16. Thereafter, the n+layer 26 is patterned and then the protective film 28 is formed thereon. In order to prevent problems such as an electrical short and crosstalk through the amorphous silicon layer 24 between the gate pads 14 and between the gate links 15, the gate insulating film 22, the amorphous silicon layer 24, the n+layer 26 and the protective film 28 are etched simultaneously to expose the transparent substrate 20. A sealant 30 is coated in a direction crossing the gate link part 15. In this case, since step coverage is generated at etched areas EA between the gate link parts 15, it is impossible to obtain a desired cell gap by the sealant 30.
FIG. 4 is an enlarged view of the data link area crossing the seal part 12 in FIG. 1, and FIG. 5 is a section view of the seal part 12 taken along the line B-B′ in FIG. 4. A data link part 33 extending from a data pad 32 comprises a gate insulating layer 22, an amorphous silicon layer 24, an “n+layer” 26, a data link electrode 34 and a protective film 28 disposed on a transparent substrate 20. The data link electrode 34 is formed integrally with the data pad 32 and the data line by depositing a data metal material and patterning it after sequentially forming the gate insulating film 22, the amorphous silicon layer 24 and the n+layer 26 and patterning the n+layer 26. A protective film 28 is provided on the data link electrode 34. In order to prevent problems such as an electrical short and crosstalk through the amorphous silicon layer 24 between the data pads 32 and between the data link part 33, the gate insulating film 22, the amorphous silicon layer 24, the n+layer 26 and the protective film 28 are etched simultaneously to expose the transparent substrate 20. A sealant 30 is coated in a direction crossing the data link part 33. In this case, since a step coverage is generated at etched areas EA between the data link parts 33, it is impossible to obtain a desired cell gap by the sealant 30 coated in a direction crossing the data link part 33.
FIG. 6 is a cut-away section view of a liquid crystal area, which is located at the opposite side of the gate link area in the picture display part 10, taken along the line C-C′ in FIG. 1. The liquid crystal area arranged with a plurality of signal wires, such as common electrode lines comprises a gate metal layer 16, a gate insulating film 22, an amorphous silicon layer 24, a n+layer 26 and a protective film 28 that are sequentially disposed on a transparent substrate 20. A sealant 30 is coated on the protective film 28.
In the conventional liquid crystal display device as described above, a step coverage exists in the etching areas between the link parts at the gate link area and the data link area, whereas a step coverage does not exist in the liquid crystal area located at the opposite side of the link area. Thus, when the sealant is coated to have a constant cell gap on a basis of the protective film which is an uppermost layer of the link area and the liquid crystal area, the sealant coated on the link area has a lower height than the sealant coated on the etched area having a step coverage. As a result, the conventional liquid crystal display device has a problem in that, since the height of the sealant is different depending on a position thereof, it has an irregular cell gap to cause a non-uniform brightness.